1. Field of the Invention
The present invention relates to analog-to-digital converters and to companding analog-to-digital converters an architecture commonly known as “single slope ADC's”. More particularly, the present invention relates to an analog-to-digital converter with digital calibration that allows programmable control of the ramp slope.
2. The Prior Art
“Single slope ADC's” is the common name given to a family of analog-to-digital converters employs a ramp voltage generator, a digital counter, an analog front end sampling section, a comparator that compares the analog input voltage with the generated ramp voltage, and a digital latch.
In a simple well-known case, the ramp voltage follows a linear function. To reduce the conversion time, the ramp voltage may be “accelerated” by using a segmented ramp function as shown in FIG. 1A. Initially, in SEGMENT(1) the ramp in FIG. 1A runs with a unit step size (STEP(1)=1*LSB or 1× ramp rate). After a specified number of clock pulses, in SEGMENT(2) the ramp rate is increased to twice the unit step size (STEP(2) or 2× ramp rate). The count at which the transition from STEP(1) to STEP(2) occurs is may be referred to as Knee(1). After counting for a certain number of steps at a 2× ramp rate, the rate is doubled again in SEGMENT(3) to STEP(4) or a 4× ramp rate. This occurs at a count that may be referred to as Knee(2). Further doubling in SEGMENT(4) results in STEP(8) at count Knee(3). At the same knee points the ramp counter increases the count steps size by 2× so that the overall ADC transfer function is linear. Companding is also done in the prior art to take advantage of the fact that the absolute level of the noise in most natural source signals increases with the signal value so that increased ADC quantization noise at larger input signal values is masked by input noise and thus the “quality” (SNR) of the ADC conversion does not decrease at higher levels. Image sensors are an example of such an application.
Persons of ordinary skill in the art will readily appreciate that the acceleration of the ramp voltage need not be constant (e.g., 2×) but may be configured in virtually any manner as warranted by the particular application. Such an alternative scheme is shown in FIG. 1B, in which the individual ramp segments SEGMENT(1) through SEGMENT(4) may have slopes that are not integer multiples of one another.
In real world implementations, non-idealities such as charge injection, amplifier offset, finite amplifier gain, and component mismatch cause each of the SEGMENT(N) sections to have unpredictable ramp rates. In the general case, the difference from the intended step size may be independent for each SEGMENT so that the composite transfer function (digital number out vs. Vin) may be non-linear. In addition, these circuit non-idealities (such as amplifier offset) may drift over the lifetime of the circuit. STEP(1) through STEP(4) and Knee(1) through Knee(3) are illustrated in SEGMENT(1) through SEGMENT(4) in FIG. 1A. A non-ideal gain for SEGMENT(3) is shown in FIG. 1A along with an ideal SEGMENT(3). It can be seen from FIG. 1A that a non-ideal gain for a single section can cause integral non-linearity (INL). Correct linearity for the ADC assumes that the gain for STEP(4) is half of that of STEP(8) and twice that of STEP(2). However, a sampled voltage during SEGMENT(4) will not have a count that corresponds linearly to a voltage sampled during STEP(2) or STEP(8). Because only part of the voltage versus count curve has non-ideal gain, integral non-linearity results. If all sections were affected in the same way, an overall gain error would occur but the transfer function would be linear.
In order to have low integral non-linearity over the entire ramp, the ramp gains (expressed in Volts/digital number or Amps/digital number) or other measured quantity for each section must be accurate. Actually, for applications such as imaging or in the general case, applications including some form of AGC function in the system, only the ratios of the gains need to be accurate for a low integral non-linearity. If the overall gain is also of interest, accurate gain for each section is desired.
A typical ramp generator 10 may be implemented as a switched capacitor integrator, shown in FIG. 2. The circuit includes a high-gain differential amplifier 12. A switched capacitor network 14 at the input of the amplifier 12 that delivers discrete packets of charge to the amplifier 12. The amplifier has a capacitive feedback network 16 configured to provide negative feedback. The feedback forces the amplifier 12 to move ramp the output voltage in order to re-balance the inputs after each packet of charge is delivered. The size of the ramp step is proportional to the input voltage from a voltage source, such as a resistor ladder, and the ratio of the input capacitance to the output capacitance. One or both of the input voltage and the size of the input capacitance may be programmable. Persons of ordinary skill in the art will understand that other methods may be used to implement the ramp generator, such as a DAC or a continuous integrator driven by a constant current source.
The ramp generator of FIG. 2 may be used in an analog-to-digital converter 20 such as the one shown in FIG. 3 in which the ramp generator 10 is associated with a counter 22 driven from the same clock source 24 as the ramp generator 10. The output count of the counter 22 has a known relationship to the ramp voltage. An analog input voltage and the ramp voltage are compared in a comparator 26 and the output of the comparator 26 is used to trigger latch 28 to latch the output of the counter 22 when the ramp voltage equals the analog input voltage. The latched count, which has a known relationship to the ramp voltage, is thus a digital representation of the measured analog input quantity.
The major sources of error in the ramp gain arise from the input offset of the ramp amplifier and a differential charge injection error. The step size of the ramp generator (and therefore the gain in V/digital number) is proportional to the amount of charge injected at each step. For each possible setting, the step size is given a constant error by the charge injection. The offset of the amplifier gives an error which is proportional to the amount of capacitance used for the particular setting. The error due to capacitance mismatch will result in an error that is proportional to the input voltage. There may also be also errors in the reference voltages Vin and Vref used by the ramp generator that must be considered. Lastly, the finite amplifier gain will cause an error that is proportional to the output voltage, which creates a non-linearity in the ramp voltage.
There are other sources of gain error such as the relative size of the feedback capacitance. These errors will be the same for all setting. The gain errors common to all settings will result in an overall gain error, but will not result in integral non-linearity due to the accelerated ramp. The inaccuracies and non-idealities described above result in circuit area and/or power and/or cost constraints which mean this approach to Analog-Digital conversion is unattractive for modern integrated circuit implementation.